Senior FPGA Network IO Architect for Ultra‑Fast AI Clusters

The Host and Network IO Team develops the full IO path from server nodes to the Cerebras WSE, including RoCE v2 interfaces, a large programmable switching fabric, and serial IO with a proprietary protocol.

As an FPGA developer on the team, you will optimize bandwidth and latency, interface with AI application IO, cluster, and embedded software teams, and contribute to multi-generational hardware designs.