Senior FPGA Engineer – ASIC/FPGA, Mission Systems

Job Duties

• Requirements capture, ASIC / FPGA digital architecture and design using RTL, timing closure, verification, and system integration
• Recommend new tools and practices for continuous improvement in the group's ASIC / FPGA design flow
• Contribute to engineering estimates for new program pursuits.
• Provide technical leadership for project design teams by breaking down work, planning activities, and reporting status

Requirements

• Typically requires a degree in Science, Technology, Engineering or Mathematics (STEM) unless prohibited by local laws/regulations and minimum 8 years prior relevant experience or an Advanced Degree in a related field and minimum 5 years of experience
• Demonstrated professional experience communicating in English (verbal and written).
• U.S. Citizenship and the ability to obtain a security clearance is required.
• RTL coding and simulation in VHDL or Verilog
• Digital circuit architecture, design, resource tradeoffs, timing analysis and timing closure
• Testbench development for the verification of RTL blocks using VHDL or System Verilog.
• Proficiency using ASIC and/or FPGA simulation and synthesis tools (e.g. Modelsim, Synplify, Quartus, Vivado, or other FPGA-specific tools)
• Experience with best practice chip-level verification techniques and languages (e.g. constrained random, functional coverage, SystemVerilog)
• Design for Test (DFT) and manufacturability issues
• Experience with Unix, scripting, C/C++, and/or Perl

Core Competencies

Expertise in ASIC and FPGA digital architecture and design, including RTL coding and simulation in VHDL or Verilog, with a strong focus on timing closure and verification. Proven ability to provide technical leadership and improve design processes through innovative tools and practices.

Highest-signal resume keywords

• RTL Coding and Simulation in VHDL or Verilog
• Digital Circuit Architecture and Design
• ASIC and FPGA Simulation and Synthesis Tools
• Testbench Development for RTL Verification
• Technical Leadership in Project Design Teams

ATS Optimization Keywords

Hard Skills

• RTL Coding
• VHDL
• Verilog
• Digital Circuit Design
• Timing Analysis
• Testbench Development
• System Verilog
• C/C++
• Perl
• Unix

Soft Skills

• Communication in English

Certifications & Qualifications

• U.S. Citizenship
• Ability to Obtain Security Clearance

Industry Keywords

• ASIC Design
• FPGA Design
• Design for Test (DFT)
• Chip-Level Verification Techniques
• Functional Coverage

Tools & Technologies

• Modelsim
• Synplify
• Quartus
• Vivado