Senior FPGA Digital Engineer (Secret Clearance)

Northrop Grumman Space Systems in Chandler, AZ is seeking a Staff FPGA Digital Engineer to support the EO Group within Launch Vehicles. You will apply advanced FPGA engineering principles, lead design challenges, and develop high-level test benches for timing-critical FPGA designs.

The role requires mastery of VHDL/Verilog, extensive Xilinx FPGA/SoC experience, and verification with OSVVM/UVM and Questa/ModelSim. Travel up to 10% may be required and DoD Secret clearance is required.