Senior FPGA Design Engineer — Memory Test Systems

Teradyne’s Memory Test Division (MTD) seeks an FPGA Design Engineer to support cutting-edge memory test solutions. You will architect FPGA designs, guide junior engineers, and translate customer requirements into robust, scalable implementations.

The role demands strong digital design, Verilog, and FPGA tool-flow expertise, with occasional travel and a focus on delivering reliable, high-quality instruments.