Senior FPGA Design & Analysis Engineer (Versal/Verilog)

PDS Defense, Inc. in El Segundo, CA is seeking an Elect Design and Analy Engr 5 for FPGA/ASIC design work. The role focuses on FPGA top-level design, IP integration, synthesis, timing closure, and device programming, primarily Versal/UltraScale families.

The position requires on-site work in El Segundo, and candidates must hold an active U.S. security clearance. Ideal for engineers with strong digital hardware fundamentals and independent work style.