Senior FPGA Debug & Verification Architect

191 Altera Corporation is seeking a Sr. Debug Design Verification Engineer responsible for Design for Debug architecture verification tasks, including creating test cases and test benches using UVM methodology. Candidates must have a minimum of 8 years of experience in complex ASIC designs and proficiency in SystemVerilog.

The role includes pre-silicon system verification and requires strong communication skills to coordinate with cross-functional teams. The salary range for this position is between $149,100 and $215,000 USD.