Senior FPGA DDR & IO Subsystem Architect

A leading innovator in FPGA technology is seeking an FPGA DDR and IO Subsystem Architect in San Jose, California. In this technical leadership role, you will define architecture for high-speed external memory and general-purpose IO subsystems. The ideal candidate will have over 10 years of experience in RTL design and expertise in DDR technologies. This opportunity offers a competitive salary range of $200,400 - $286,000 USD.
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