Senior FPGA/ASIC Design Lead – RTL, Timing & Verification

Jobtailor in Aguadilla, PR seeks an experienced ASIC/FPGA engineer to lead RTL design, timing closure, and verification. You will work on RTL coding in VHDL/Verilog, develop testbenches, and drive architectural decisions with emphasis on design-for-test and manufacturability.

Applicants should hold a STEM degree with extensive related experience, strong English communication, and eligibility for security clearance. Proficiency with Modelsim, Synplify, Quartus, and Vivado is required.