Senior Fab Yield Engineer

The Senior Wafer Fab Yield Engineer is responsible for driving systematic yield improvement across semiconductor wafer fabrication. This position analyzes manufacturing, inline metrology, defect, wafer-level electrical test, and process data to identify yield-loss mechanisms, determine root causes, and lead implementation of sustainable corrective actions.

The engineer serves as a senior technical resource connecting fab process performance to device and product yield. The role works cross-functionally with Process Engineering, Equipment Engineering, Process Integration, Product/Test Engineering, Failure Analysis, Quality, and Manufacturing to improve yield, reduce variability, and accelerate resolution of complex manufacturing problems.

Required Qualifications

• Bachelor's degree in Electrical Engineering, Materials Science, Physics, or a related technical discipline.
• Significant engineering experience in semiconductor wafer fabrication, preferably involving yield, process integration, process engineering, product engineering, device engineering, or failure analysis.
• Strong understanding of semiconductor wafer fabrication processes and the relationship between process variation, device characteristics, defects, and electrical yield.
• Demonstrated ability to perform statistical analysis and solve complex manufacturing problems using large manufacturing datasets.
• Experience with statistical/data-analysis tools such as JMP, or comparable platforms.
• Working knowledge of SPC, DOE, process capability, correlation/regression, hypothesis testing, and structured root-cause analysis.
• Ability to communicate complex technical conclusions clearly to engineering and manufacturing organizations.
• Demonstrated ability to lead cross-functional technical problem-solving efforts.

Preferred Qualifications

• Master's degree in Electrical Engineering, Materials Science, Applied Physics, or related discipline.
• Experience correlating inline process/defect data → WAT/electrical data → wafer-sort/final yield.
• Experience with wafer-map and spatial-pattern analysis.
• Experience with semiconductor defect inspection and/or physical failure analysis.
• Experience creating automated yield-analysis or data-mining tools.
• Knowledge of semiconductor device physics and electrical test structures.
• Experience supporting technology or product ramps in a high-volume wafer fabrication environment.

• annual bonus + LTI program
• Relocation assistance
• Generous PTO, holidays, birthday off, companywide "holiday"
• Full benefits