Senior DV Engineer – Space ASICs

E-Space, based in Saratoga, CA, is seeking Digital Design Verification Engineers to verify our custom ASICs for satellite and wireless telephony. The role requires Verilog, SystemVerilog and UVM expertise, with VHDL knowledge a plus. This is a full-time exempt position in our Saratoga office.

The base pay target is $120,000 to $220,000 annually, with total compensation determined by experience and skills. Sponsorship is not available for this location at this time.