Senior DV Engineer, SoC/IP (SystemVerilog/UVM)

Apple, Inc. is seeking a design verification engineer to drive pre-silicon validation for IP blocks and full SoC portions. You will define DV methodology, build verification environments with stimulus and checkers, and write tests.

The role emphasizes scalability, regression debugging, and leveraging LLMs to improve quality and speed. The candidate should have a strong background in SystemVerilog/UVM, verification methodologies, and experience with power-aware techniques.