Join E‑Space as a Digital Design Verification Engineer to verify custom ASICs for satellite and wireless telephony. You will use Verilog, SystemVerilog, and UVM to develop and maintain verification environments.
Qualifications
- HDL & Verification Methodology.
- Proficiency in Verilog and SystemVerilog.
- Working knowledge of UVM architecture and methodology.
- Ability to write verification tests within an existing environment.
- Some experience scripting in Perl, Python, or bash.
- 4+ years of design verification experience in the semiconductor industry.
Compensation & Benefits
Full‑time, exempt position based out of our Saratoga office. Target base pay for this role is $120,000 – $220,000 annually. Total compensation will be determined by relevant job‑related knowledge, skills, and experience.
- Opportunity to really make a difference.
- Sustainability at our core.
- Fair and honest workplace.
- Innovative thinking is encouraged.
- Competitive salaries.
- Continuous learning and development.
- Health and wellness care options.
- Financial solutions for the future.
- Optional legal services (US only).
- Paid holidays.
- Paid time off.
E‑Space is not currently able to provide employment sponsorship for candidates who do not hold work authorization for the location of this role.
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