E-Space is seeking Digital Design Verification Engineers to verify our custom ASICs for satellite and wireless telephony. You will write and run verification tests using Verilog, SystemVerilog and UVM in a high‑growth space environment.
Based in our Saratoga office, this full-time, exempt role offers a base pay range of $120,000–$220,000 annually, with compensation determined by experience and impact. A sponsorship note: we cannot sponsor visas for this location at this time.
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