Senior Digital Layout Engineer for Next‑Gen ASICs

Apple Inc. in Beaverton, Oregon, seeks an experienced Digital Layout Designer to craft state-of-the-art ASIC layouts.

You will design complex custom digital macros, review floorplans, and work with the circuit and CAD teams to produce robust physical designs for next-generation chips. Ideal candidates bring a decade of layout experience, strong RC delay and electromigration knowledge, and proficiency with CALIBRE/ Mentor Graphics or Cadence tools.