Senior Logic Design EngineerAs a Senior Logic Design Engineer, you will be responsible for:Developing micro-architecture specification of the logic circuit from reading and comprehending the Product Requirement Document (PRD)Developing the Register Transfer Level (RTL) design from the micro-architecture specification using Verilog or SystemVerilog as the HDLDeveloping standalone testbenches to verify the RTL behaviorWriting and verifying SystemVerilog Assertions (SVA) for a designWriting timing constraints and clock definition for synthesis and place and route toolsRunning industry-standard synthesis tools (e.g., Genus or Design Compiler) and being able to fix the timing problems if they ariseUnderstanding various design tradeoffs including timing/area/power and knowing how to improve themReading and understanding the Static Timing Analysis (STA) reports from an industry-standard STA tool (e.g., Prime Time)Cross functional interactions and communication with various teams including analog, verification, backend, system and test engineering teamsPost-Si bring-up, validation and debuggingQualifications & Requirements (Education must be included):Master's degree in electrical engineering plus 5 years of relevant work experience in the industryExcellent verbal and written communication skills in EnglishProficient in Verilog and SystemVerilogExpertise in digital logic design fundamentals such as clock divider circuits, multi-clock logic designs, CDC, FIFO, FSM, etcExperience in designing mixed-signal digital logicBasic understanding of Discrete time Signal Processing theory, FIR and IIR filter designSolid experience in digital design flow including RTL design, synthesis, timing constraints, and STASkilled in scripting languages Perl/Tcl/PythonDesired Characteristics & Attributes:PhD in electrical/computer engineering plus 3 years of relevant industry experience2-5 years of experience in designing high-precision digital arithmetic logic and Digital Signal Processing2-5 years of experience in designing Digital Phase-Locked Loops (DPLL)Experience in complex FSM designFamiliarity with MATLAB, Simulink or any other high-level modeling toolsExperience in low-power digital design flowBasic understanding of the Control Theory