Astera Labs in San Jose, California seeks Principal Digital Design Engineers with micro-architecture and front-end circuit design experience to work on high-performance network controllers. You will contribute to RTL, synthesis, IP integration, and block-level verification for PCIe, Ualink, Esun, Ethernet, and related protocols.
The role requires 8+ years in SoC/Silicon, DFT, UVM verification, and ownership from architecture to GDS.
#J-18808-LjbffrSenior Digital Design Engineer – High-Speed Network SoC in san jose at Unknown Company
This position is listed as full time and onsite.