Fortune 500 is seeking a Digital Mixed-Signal Lead to steer the architecture, RTL design, and clocking IP for advanced digital control infrastructures in mixed-signal subsystems. You will own the digital logic definitions driving PLLs, FLLs, and DLLs, collaborating closely with analog and verification teams.
The role demands 8+ years in digital ASIC design, deep SystemVerilog RTL expertise, and a track record of tapeouts across advanced nodes.
#J-18808-LjbffrSenior Digital Clocking Architect & RTL Lead in san francisco at Unknown Company
This position is listed as full time and onsite.