Senior Digital ASIC Design Engineer - High-Speed SoCs

Teradyne seeks a Senior ASIC Digital Design Engineer in Agoura Hills, CA to develop complex mixed-signal ASICs for next‑generation semiconductor test systems. You will work with architects, analog designers, verification, and physical design teams, driving digital design from architecture to silicon bring‑up.

You will own critical subsystems, influence technical direction, and mentor junior engineers, leveraging strong Verilog RTL expertise and robust collaboration across cross‑functional teams.