Entrada Ventures is seeking a Senior DFT Verification Engineer to drive robust verification for ASIC DFT logic across planning, development, and closure. You will build scalable environments, guide test strategies, and collaborate with DFT design and manufacturing teams to deliver high-quality silicon.
The role emphasizes hands-on SystemVerilog, UVM, and modern verification workflows, plus experience with scan/ATPG, JTAG, MBIST, and tester formats.
#J-18808-LjbffrSenior DFT Verification Engineer for ASICs in palo alto at Unknown Company
This position is listed as full time and onsite.