- Run formal verification between synthesized netlist and post DFT netlist.
- Generate DFT constraints for backend and Primetime.
- Provide BE team with post DFT netlist and associated constraints.
- Validation plan and test development.
- Generate ATPG Test Patterns.
- Block level and soc level patten generation.
- Monitor test coverage and pattern counts.
- Run ATPG and pattern verification on DFT inserted netlist
- MBIST pattern RTL and gate level validation.
- Run full MBIST, scan pattern generation and verification (both pre and post layout netlist)
- After chip top netlist is available, all block MBIST, scan pattern generation and verification should be run from top level.
Senior DFT Engineers in austin at Unknown Company
This position is listed as full time and onsite.