Senior DFT Engineer: ASIC Test & Silicon Bring-Up

Normal Computing is seeking a Design-for-Test (DFT) Engineer to own DFT architecture for next-generation ASICs, driving scan/ATPG, MBIST, and boundary-scan strategies from RTL through tapeout and silicon bring-up.

You will collaborate with RTL, verification, physical design, and silicon product engineering teams, establishing scalable DFT flows and partnering with external partners to deliver production-ready test patterns and collateral. Strong leadership and scripting skills are essential.