Senior DFT Engineer, ASIC/SoC Test & Signoff

Celero Communications, Inc. in Irvine, CA is seeking a Principal DFT Engineer to lead design-for-test strategies for ASIC and SoC products.

You will collaborate with RTL, verification, physical design, product, and manufacturing to implement robust DFT methods that enable high-quality, high-volume production. The role requires 8+ years in ASIC/SoC DFT, expertise in scan, ATPG, MBIST, JTAG, and experience with Synopsys, Siemens, and Cadence tools.