Cadence is seeking a SoC/ASIC Digital Design Engineer with extensive experience in Design for Test (DFT). The role emphasizes scan chain insertion, compression scan technologies, MBIST, and ATPG pattern generation, with a preference for hands-on synthesis, verification, and debugging Verilog test benches.
US citizenship is preferred. Ideal candidates will have deep knowledge of DFT insertion flows, JTAG 1149.1/6, IEEE1500/IEEE1687, and the ability to work independently in a fast-paced project
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