Senior DFT/ATPG Engineer - SoC & Memory

Katalyst-Healthcares- in Santa Clara, CA, seeks an experienced Design for Test (DFT) and ATPG engineer to support advanced SoC/ASIC programs. The role emphasizes hands-on DFT/ATPG development, pattern generation, analysis, and debugging across complex semiconductor projects.

You will work with MBIST architectures, I/O test methodologies, clock DFT concepts, and RTL fundamentals while collaborating in a fast-paced, high-performance team environment.