Senior DFT Architect - Multi-Chip SoC

Eridu, a Silicon Valley hardware startup, seeks an experienced engineer to define the DFT architecture for a multi-chip SOC, covering test design, SDC constraints, and ATPG. You will work with RTL and gate-level simulations and oversee high-coverage scan techniques, including LBIST and streaming.

Expertise with Mentor/Synopsys test tools is preferred. Based in Saratoga, CA, the role offers a base salary in the range of 195,000–250,000 USD per year, with compensation determined by skills and