Senior Design Verification Engineer - SystemVerilog/UVM

Themesoft Inc. is seeking an experienced verification engineer based in Austin, TX. The ideal candidate will have over 8 years of experience, particularly in architecting and developing complex verification environments using SystemVerilog. Responsibilities include writing tests and sequences, coordinating with RTL engineers, and driving formal verification metrics. Candidates should possess a Bachelor's or Master's degree in Computer Engineering or Electrical Engineering. Familiarity with verification tools such as VCS and Cadence is preferred.
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