Senior Design Verification Engineer – SoC Pre-Silicon

Apple Inc. is seeking an outstanding Design Verification Engineer to enable first silicon for IP designs. You will develop DV methodology, write test plans, and build verification environments in SystemVerilog/UVM to stress the design.

This role focuses on bug-free silicon, regression debugging, and sign-off readiness. Proficiency with LLMs for efficiency and experience in UPF or similar methodologies are advantageous; deep knowledge of OOP, SystemVerilog, and UVM is expected.