Senior Design Verification Engineer

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Triple Crown is a leading provider of hardware, embedded, software, and mechanical engineering talent. Businesses and technology teams rely on our ability to rapidly place the developers, architects, coders, and designers who engineer digital transformation and growth.

Job Type: Contract

Duration: 6+ Months

Location: Remote or Onsite in Santa Clara, CA

Requirement: 5+ years of relevant experience

Overview

We are seeking a highly skilled Design Verification Engineer to join our growing team. The ideal candidate will have strong fundamentals in SystemVerilog/UVM and hands-on experience working on multiple projects, ranging from IP Block-level to SoC/Full Chip Verification . This role requires a proactive engineer who can contribute across different verification environments and communicate effectively about past experiences and responsibilities.

Responsibilities

• Strong fundamentals in SystemVerilog/UVM-based verification .
• Experience with IP block-level and SoC/full-chip verification .
• Hands-on knowledge of standard protocols such as Ethernet, Memory, AXI, AMBA, and Processors .
• Proficiency in C programming for test development and debugging.
• Ability to clearly articulate recent project experience, roles, and responsibilities in verification environments.
• Strong problem-solving and debugging skills.

Qualifications

• UVM-Based Verification
• Soc
• Full Chip Verification
• IP Block-level
• C Programming
• Health, Dental and Vision Insurance
• 401k

Seniority level

• Mid-Senior level

Employment type

• Contract

Job function

• Engineering

Industry

• Semiconductor Manufacturing

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Note: This description reflects the role and its requirements as provided. Salary postings and related location-specific notices have been removed for clarity.