AMD is seeking a skilled Design Verification Engineer in Santa Clara, CA, to drive verification closure on complex ASIC designs. The role requires hands-on verification expertise and strong debugging skills across architecture and RTL.
The ideal candidate will develop UVM-based testbench architectures, manage execution of verification plans, and collaborate cross-functionally to ensure quality deliverables. Rewards include a collaborative culture and opportunities for professional growth.
#J-18808-LjbffrSenior Design Verification Engineer, Networking SoC in santa clara at Unknown Company
This position is listed as full time and onsite.