Senior Design Verification Engineer - Full-Chip & FPGA

Redolent Infotech Pvt. Ltd. in Folsom, CA seeks a Design Verification Engineer to drive full-chip verification using industry-standard methodologies.

You will develop UVM/OVM/VMM test benches, verify interfaces such as PCIe, NoC/AXI, DDR4, and work with tools like Synopsys VCS, Cadence IES, and formal checkers.

Candidates should have strong knowledge of verification techniques, SystemC-based modeling, and FPGA programming experience.