We are seeking a Physical Design Engineer to work on a high‑performance L2 cache unit designed to support cutting‑edge AI processing elements.
Location(s)
- Las Vegas, NV
- Sunnyvale, CA
Responsibilities
- Working on high performance L2 Cache unit serving the needs of state‑of‑the‑art AI processing elements.
Qualifications
- Requires 2 to 4 years of experience (will consider bright individuals even with lower experience) and the following skills:
- Understanding of high speed and low power processor pipeline designs / ASICs / SoCs and multi‑core designs.
- Strong understanding of computer architecture.
- Experience with cache controller designs, understanding of cache coherency protocols, cache hierarchy.
- Logic design experience with state of the art deep sub‑micron technologies specifically low power design techniques.
- Verilog / SystemVerilog / synthesis / Static Timing Analysis / CDC / lint.
- Knowledge of ARM and x86 and multicore processor designs is a plus.
- Knowledge of programming languages C, scripting (Perl / shell / python / awk) is a plus.
- Knowledge of cache design and coherency protocols.
Benefits
- Competitive salary and benefits package.
- Opportunities for professional development and advancement.
- International environment and further career progression.
- Getting in touch with bleeding‑edge technology.
- Collaborative and supportive work environment.