Develop logic design, register transfer level (RTL) coding, and simulation for SoC designs while integrating IP blocks and subsystems into full chip SoC or discrete component designs.
Participate in defining architecture and microarchitecture features of the blocks being designed and perform quality checks across various logic design aspects ranging from RTL to timing/power convergence.
Apply various strategies, tools, and methods to write RTL and optimize logic to meet power, performance, area, and timing goals while ensuring design integrity for physical implementation.
Work closely with verification teams, review verification plans and implementation to ensure design features are verified correctly, resolving and implementing corrective measures for failing RTL tests.
Follow secure development practices to address security threat models and security objectives within the design, work with IP providers to integrate and validate IPs at the SoC level, and drive quality assurance compliance for smooth IP/SoC handoff.
Requirements
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or Computer Science.
7+ years of experience in RTL design and implementation for ASIC/SoC development.
Proven ability to solve complex design challenges such as clock domain crossings, power optimization, and timing closure.
Hands‑on experience with SoC system integration and multicore CPU subsystem design.
Strong knowledge of standard bus protocols (AXI, AHB, etc.) and embedded processor architectures.
Expertise in high-speed and low-power design techniques.
Proficiency in scripting (Python, TCL, etc.) for automation and design flow optimization.
Familiarity with industry standard EDA tools, including simulators (VCS, Questa, Xcelium), lint tools (Spyglass), and FPGA prototyping tools (Xilinx Vivado, Altera Quartus II).
Ability to thrive in a dynamic environment with evolving requirements.