TSMC - Taiwan Semiconductor Manufacturing Company Limited in San Jose, CA seeks an experienced engineer to advance defect modeling, testing, and analysis for next‑gen 2.5D/3D packaging. This role emphasizes developing models, running SPICE simulations, and collaborating with design, process, test, and reliability teams to push innovative approaches.
You will contribute to methodologies for defect detection, test strategy optimization, and industry-leading packaging solutions, with visa
#J-18808-LjbffrSenior Defect Modeling & 3D Packaging Lead in ca at Unknown Company
This position is listed as full time and onsite.