Altera in San Jose is seeking a highly skilled DDR5 / LPDDR5 Memory Validation Engineer to lead validation and debug activities for advanced memory interfaces on cutting-edge FPGA devices.
The role requires significant industry experience in memory subsystem validation and strong collaboration skills across multiple teams. The salary range is $149,100 - $215,000 USD, with additional incentive opportunities.
#J-18808-LjbffrSenior DDR5/LPDDR5 Memory Validation Lead in san jose at Unknown Company
This position is listed as full time and onsite.