Google in Mountain View, CA, USA seeks a Senior CPU RTL Design Engineer to advance CPU cache subsystems with RTL focus. You will collaborate across performance, architecture, and software teams to evaluate trade-offs and optimize microarchitectures for future CPUs.
Requires a Bachelor's in a related field and 8 years' experience with SystemVerilog, Lint, UPF, and CPU cache designs. Google offers a strong compensation package and equity as part of total rewards.
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