Jobtailor is seeking a senior hardware design engineer to drive physical design for customized CPUs. You will translate RTL to GDS, manage synthesis, place & route, and timing analysis while ensuring signoff and formal verification.
The role emphasizes power, frequency, and area optimization and close collaboration with EDA vendors. Ideal candidates bring 4–6+ years of VLSI experience, strong timing analysis, and low-power design skills, with familiarity in x86 architectures and scripting in
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