Senior CPU CDC/RDC Engineer – SystemVerilog & RTL

Apple Inc. in Santa Clara is seeking a senior hardware verification engineer to own the CDC/RDC sign-offs for CPU designs, collaborate with RTL and DV teams, and drive robust STA checks across multi-clock domains.

The role requires deep Verilog/SystemVerilog expertise, experience with CDC/RDC, EDA tools such as Synopsys or Real Intent, TCL/Perl scripting, and a track record of delivering safe, scalable designs in complex SoC environments.