Trinus Corporation is seeking a senior IC layout engineer with 10+ years of custom IC layout experience, including memory IP. You will contribute to SRAM design, memory compiler efforts, and advanced CMOS node initiatives.
Candidates will master Cadence Virtuoso, perform DRC/LVS debugging, and collaborate with circuit, physical, CAD, and foundry teams. Strong communication and mentorship skills are essential; knowledge of layout automation or AI tools is a plus.
#J-18808-LjbffrSenior CMOS/FinFET Memory Layout Engineer in santa clara at Unknown Company
This position is listed as full time and onsite.