Senior C++ Compiler Architect for AI Chip Verification

Cadence Design Systems seeks a Senior Engineer to evolve the SystemVerilog compiler for next-generation EDA tools, enabling scalable AI chip designs. You will craft high-performance front-end and IR/code generation components, applying multi-threading and memory optimizations on large-scale designs.

With 5+ years in compiler development, you will leverage C++, SystemVerilog, and LLVM within a leading semiconductor technology environment.