A leading technology firm is seeking an experienced engineer in San Diego to manage the complete verification lifecycle for digital power IPs. The ideal candidate has a Bachelor's degree in Engineering or Science and over four years of experience in ASIC design and verification, with proficiency in SystemVerilog and related methodologies. This role offers a competitive salary and dynamic work environment.
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Senior ASIC Verification Engineer SystemVerilog/UVM & Power IP in san diego at Unknown Company
This position is listed as full time and onsite.