Broadcom in Irvine, California is seeking a Constrained Random Design Verification Engineer to join a stable team developing silicon products for Ethernet systems. The role involves verifying new designs and collaborating with global teams to develop cutting-edge products.
The ideal candidate will have a Bachelor's degree with 12+ years of experience, or a Master's with 10+, or a PhD with 3+. Strong teamwork, System Verilog and UVM skills are essential. The position includes a competitive salary and comprehensive benefits package.
#J-18808-LjbffrSenior ASIC Verification Engineer (SV/UVM) – Equity & Bonus in irvine at Unknown Company
This position is listed as full time and onsite.