CesiumAstro is seeking a Principal ASIC Functional Verification Engineer to join the Design Verification team. You will design and implement verification test benches for system, chip and block level verification using SystemVerilog, UVM, OVM or VMM and develop functional coverage plans.
Requirements include a BS in CS/EE or related field with 10+ years of experience (or 8+ years with a Masters), strong knowledge of SystemVerilog and verification methodologies, and excellent communication
#J-18808-LjbffrSenior ASIC Verification Engineer (SoC) – Testbench Lead in aliso viejo at Unknown Company
This position is listed as full time and onsite.