Senior ASIC Timing Engineer — Hybrid, Equity Eligible

NVIDIA is seeking a Senior ASIC Timing Engineer to drive timing analysis and closure for GPUs, CPUs, LPUs, and SoCs across multiple levels. You will collaborate with RTL, DFX, and Clocks teams to define timing constraints and drive convergence while optimizing timing and power.

A strong background in STA and ECOs is required. The role emphasizes hands-on full-chip/stage timing, crosstalk/noise analysis, and flow improvements for deeper sub-micron nodes, with hybrid work options and competitive