Senior ASIC Timing & STA Engineer – Lead SoC Signoff

Marvell is seeking an experienced Senior STA Engineer in Irvine, CA to develop and validate timing constraints for intricate SoC designs. You will collaborate with Architecture, RTL, DFT, and Analog teams to implement timing signoff, ECOs, and scripts for streamlined flows.

You will perform static timing analysis with Primetime, tackle signoff methodology, and optimize QoR across all modes. This role emphasizes automation, scripting, and thorough documentation to drive continuous improvement.