Senior ASIC STA Engineer - Multi-Clock SoC Timing Expert

A leading semiconductor company is seeking an ASIC Design STA engineer in San Jose, California. This role involves building and verifying timing constraints for large SoCs, requiring expertise in SDC development and EDA tools, particularly Synopsys Design Compiler and Primetime. Candidates should have a degree in computer or electrical engineering and strong analytical skills. The company offers a collaborative culture and a commitment to equal opportunity employment.
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