MatX is seeking silicon physical design engineers to develop high-performance, energy-efficient silicon for GenAI products in Mountain View, CA. You will drive PD across blocks, subsystems, and full-chip scope from RTL to GDSII, owning schedules and sign-offs.
The role requires 8+ years in ASIC PD, strong collaboration with Design/DFT teams, and proficiency in Perl, Python, and TCL. Competitive compensation and comprehensive benefits offered.
#J-18808-LjbffrSenior ASIC/SOC Physical Design Engineer in mountain view at Unknown Company
This position is listed as full time and onsite.