Senior ASIC/RTL Verification Engineer

A leading technology solutions provider is seeking an experienced ASIC/RTL Design Engineer for a 12-month contract role. Responsibilities include developing verification tests, debugging failures, and collaborating with engineering teams. The ideal candidate has over 10 years of ASIC design verification experience and is proficient in C/C++, Verilog, and System Verilog. This position is W2 only, located in California.
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