Senior ASIC Physical Design Technical Lead

Senior ASIC Physical Design Technical Lead

Join Cisco's Common Hardware Group (CHG) as a key contributor in designing and developing advanced ASICs for networking hardware. This role focuses on fullchip floorplanning, RTL-to-GDSII implementation, and collaboration with various teams to enhance design methodologies. Ideal candidates will have extensive experience in physical design and a passion for innovation in the AI era.

Responsibilities:

• Understand architecture and IP placement constraints for fullchip floorplan.
• Collaborate with system and package design teams to incorporate requirements into the floorplan.
• Perform hierarchical implementation flow including partitioning, pin assignment, and clock planning.
• Execute RTL-to-GDSII implementation focusing on performance, power, and die size optimization.
• Analyze tool flows and methodologies to identify and implement efficiency improvements.
• Work closely with RTL, DFT, implementation, and EDA vendors to enable best-in-class design methodology.
• Utilize low-power design methodologies and collaborate with foundry and IP vendors for signoff methodologies.

Qualifications:

• Bachelor’s Degree in Electrical Engineering with 12+ years of Physical Design experience, or Master’s Degree with 8+ years, or PhD with 5+ years.
• Experience with Fullchip activities and RTL-to-GDSII flow in advanced process technologies (7nm/5nm/3nm).
• Proficiency with EDA tools such as Innovus, Tempus/Primetime, Redhawk/Voltus, or Calibre/Pegasus.

Skills:

• Experience in hierarchical design, timing closure, and power integrity analysis.
• Knowledge of static timing analysis and defining timing constraints.
• Expertise in fullchip floor-planning and power grid planning.
• Familiarity with custom clock designs at the chip level.
• Proficiency in Python and AI tools for productivity improvements.

Find the Right Semiconductor Partner

• ASIC Design Services
• Verification
• Packaging & Wafer
• Semiconductor IP

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