Senior ASIC Physical Design Lead - RTL-to-GDSII Expert

Cisco's Common Hardware Group in San Jose, CA is seeking a Senior ASIC Physical Design Technical Lead to drive fullchip floorplanning and RTL-to-GDSII implementation for networking ASICs.

The role requires extensive physical design experience, collaboration with RTL, DFT, EDA vendors, and applying low-power methodologies to optimize performance, power, and die size in advanced node processes.