Jobtailor seeks an accomplished Physical Design Engineer to lead fullchip floorplanning and hierarchical implementation for advanced node tapeouts. You will collaborate across RTL, DFT, and EDA teams to optimize performance, power, and die size while leveraging AI tools to boost productivity.
Ideal candidates have extensive experience with RTL2GDSII flows, clock mesh design, and signoff methodologies for 7nm/5nm/3nm processes, and are proficient in Python scripting.
#J-18808-LjbffrSenior ASIC Physical Design Lead — Fullchip & Clock Mesh in california at Unknown Company
This position is listed as full time and onsite.